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A3988 Quad DMOS Full Bridge PWM Motor Driver
Features and Benefits
36 V output rating 4 full bridges Dual stepper motor driver High current outputs 3.3 and 5 V compatible logic supply Synchronous rectification Internal undervoltage lockout (UVLO) Thermal shutdown circuitry Crossover-current protection Low profile QFN package
Description
The A3988 is a quad DMOS full-bridge driver capable of driving up to two stepper motors or four dc motors. Each full-bridge output is rated up to 1.2 A and 36 V. The A3988 includes fixed off-time pulse width modulation (PWM) current regulators, along with 2- bit nonlinear DACs (digital-to-analog converters) that allow stepper motors to be controlled in full, half, and quarter steps, and dc motors in forward, reverse, and coast modes. The PWM current regulator uses the Allegro(R) patented mixed decay mode for reduced audible motor noise, increased step accuracy, and reduced power dissipation. Internal synchronous rectification control circuitry is provided to improve power dissipation during PWM operation. Protection features include thermal shutdown with hysteresis, undervoltage lockout (UVLO) and crossover current protection. Special power up sequencing is not required. The A3988 is supplied in two packages, EV and JP, with exposed power tabs for enhanced thermal performance. The EV is a 6 mm x 6 mm, 36 pin QFN package with a nominal overall package height of 0.90 mm. The JP is a 7 mm x 7 mm 48 pin LQFP. Both packages are lead (Pb) free, with 100% matte tin leadframe plating.
Packages
Package EV, 36 pin QFN 0.90 mm nominal height with exposed thermal pad Package JP, 48 pin LQFP with exposed thermal pad
Approximate scale
0.1 F 50 V VCP CP1 CP2
0.1 F 50 V VBB1 VBB2 100 F 50 V
VMOTOR 32 V 0.22 F 50 V
PHASE1 I01 I11 PHASE2 Microprocessor I02 I12 PHASE3 I03 I13 PHASE4 I04 I14 VREF1 VREF VREF2 VREF3 VREF4 VDD VDD 3.3 V
OUT1A OUT1B
A3988
OUT2A OUT2B OUT3A OUT3B OUT4A OUT4B SENSE2 RS2 SENSE1 RS1 SENSE3 RS3 SENSE4 RS4 Bipolar Stepper Motors
Figure 1. Typical application circuit A3988DS, Rev.3
A3988
Selection Guide
Part Number A3988SEV-T A3988SEVTR-T A3988SJP-T
Quad DMOS Full Bridge PWM Motor Driver
Package 36 pin QFN with exposed thermal pad 36 pin QFN with exposed thermal pad 48 pin LQFP with exposed thermal pad 61 pieces per tube 1500 pieces per reel 250 pieces per tray Packing
Absolute Maximum Ratings
Characteristic Load Supply Voltage Logic Supply Voltage Output Current Symbol VBB Pulsed tw < 1 s VDD IOUT May be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or a Junction Temperature of 150C. Pulsed tw < 1 s Logic Input Voltage Range SENSEx Pin Voltage VREFx Pin Voltage Operating Temperature Range Junction Temperature Storage Temperature Range VIN VSENSEx Pulsed tw < 1 s VREFx TA TJ(max) Tstg Range S Notes Rating -0.5 to 36 38 -0.4 to 7 1.2 Units V V V A
2.8 -0.3 to 7 0.5 2.5 2.5 -20 to 85 150 -40 to 125
A V V V V C C C
Thermal Characteristics (may require derating at maximum conditions)
Characteristic Package Thermal Resistance Symbol RJA Test Conditions EV package, 4 layer PCB based on JEDEC standard JP package, 4 layer PCB based on JEDEC standard Min. Units 27 23 C/W C/W
Power Dissipation versus Ambient Temperature
5500 5000 4500 4000
JP Package 4-layer PCB (R JA = 23 C/W)
Power Dissipation, PD (mW)
3500 3000 2500 2000 1500 1000 500 0 25 50 75 100 125 Temperature (C) 150 175
EV Package 4-layer PCB (R JA = 27 C/W)
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A3988
Quad DMOS Full Bridge PWM Motor Driver
Functional Block Diagram
0.1 F 50 V
0.1 F 50 V
100 F 50 V 0.22 F 50 V
To VBB2
VBB1
VCP
CP1
CP2
VDD
DMOS FULL-BRIDGE 1
VCP
VBB1
OSC
CHARGE PUMP
OUT1A
PHASE1 I01 I11 PHASE2 I02 I12 GATE DRIVE VBB1 DMOS FULL-BRIDGE 2 Control Logic Bridges 1 and 2
OUT1B
SENSE1
Sense1 VREF1 3
-
+
PWM Latch BLANKING OUT2A
VREF2
3 Sense2
+
PWM Latch BLANKING OUT2B
-
PHASE3 I03 I13 PHASE4 I04 I14 GATE DRIVE Sense3 VBB2 PWM Latch BLANKING SENSE3 Control Logic Bridges 3 and 4 VCP Sense2 SENSE2
VBB2
DMOS FULL-BRIDGE 3
OUT3A OUT3B
+
VREF3
3
-
Sense3
DMOS FULL-BRIDGE 4
VREF4 3 Sense4
OUT4A OUT4B
GND
GND
+
PWM Latch BLANKING Sense4 SENSE4
-
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A3988
Quad DMOS Full Bridge PWM Motor Driver
ELECTRICAL CHARACTERISTICS1, valid at TA = 25C, VBB = 36 V, unless otherwise noted Characteristics Load Supply Voltage Range Logic Supply Voltage Range VDD Supply Current Output On Resistance Vf , Outputs Output Leakage VBB Supply Current Control Logic Logic Input Voltage Logic Input Current Input Hysteresis VIN(1) VIN(0) IIN Vhys PWM change to source on Propagation Delay Times tpd PWM change to source off PWM change to sink on PWM change to sink off Crossover Delay Blank Time VREFx Pin Input Voltage Range VREFx Pin Reference Input Current Current Trip-Level Error3 Protection Circuits VBB UVLO Threshold VBB Hysteresis VDD UVLO Threshold VDD Hysteresis Thermal Shutdown Temperature Thermal Shutdown Hysteresis
1For 2Typical
Symbol VBB VDD IDD RDS(on) Operating Operating
Test Conditions
Min. 8.0 3.0 - - - - -20 -
Typ.2 - - 7 700 700 - - -
Max. 36 5.5 10 800 800 1.2 20 8
Units V V mA m m V A mA
Source driver, IOUT = -1.2 A, TJ = 25C Sink driver, IOUT = 1.2 A, TJ = 25C IOUT = 1.2 A Outputs, VOUT = 0 to VBB IOUT = 0 mA, outputs on, PWM = 50 kHz, DC = 50%
IDSS IBB
0.7xVDD - VIN = 0 to 5 V -20 150 350 35 350 35 300 0.7 Operating VREF = 1.5 VREF = 1.5, phase current = 100% VREF = 1.5, phase current = 67% VREF = 1.5, phase current = 33% 0.0 - -5 -5 -15 7.3 400 VDD rising 2.65 75 155 -
- - <1.0 300 550 - 550 - 425 1 - - - - - 7.6 500 2.8 105 165 15
- 0.3xVDD 20 500 1000 300 1000 250 1000 1.3 1.5 1 5 5 15 7.9 600 2.95 125 175 -
V V A mV ns ns ns ns ns s V A % % % V mV V mV C C
tCOD tBLANK VREFx IREF VERR
VUV(VBB) VUV(VBB)hys VUV(VDD) VUV(VDD)hys TJTSD TJTSDhys
VBB rising
input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin. data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for individual units, within the specified maximum and minimum limits. 3V ERR = [(VREF/3) - VSENSE] / (VREF/3).
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A3988
Quad DMOS Full Bridge PWM Motor Driver
Functional Description
Device Operation The A3988 is designed to operate two
stepper motors, four dc motors, or one stepper and two dc motors. The currents in each of the output full-bridges, all N-channel DMOS, are regulated with fixed off-time pulse width modulated (PWM) control circuitry. Each full-bridge peak current is set by the value of an external current sense resistor, RSx , and a reference voltage, VREFx . If the logic inputs are pulled up to VDD, it is good practice to use a high value pull-up resistor in order to limit current to the logic inputs, should an overvoltage event occur. Logic inputs include: PHASEx, I0x, and I1x. Note: It is critical to ensure that the maximum rating of 500 mV on each SENSEx pin is not exceeded.
Fixed Off-Time The internal PWM current control circuitry
uses a one shot circuit to control the time the drivers remain off. The one shot off-time, toff , is internally set to 30 s.
Blanking This function blanks the output of the current sense
comparator when the outputs are switched by the internal current control circuitry. The comparator output is blanked to prevent false detections of overcurrent conditions, due to reverse recovery currents of the clamp diodes, or to switching transients related to the capacitance of the load. The stepper blank time, tBLANK , is approximately 1 s.
Internal PWM Current Control Each full-bridge is controlled by a fixed off-time PWM current control circuit that limits the load current to a desired value, ITRIP . Initially, a diagonal pair of source and sink DMOS outputs are enabled and current flows through the motor winding and RSx. When the voltage across the current sense resistor equals the voltage on the VREFx pin, the current sense comparator resets the PWM latch, which turns off the source driver. The maximum value of current limiting is set by the selection of RS and the voltage at the VREF input with a transconductance function approximated by: ITripMax = VREF / (3xRS) Each current step is a percentage of the maximum current, ITripMax. The actual current at each step ITrip is approximated by: ITrip = (% ITripMax / 100) ITripMax where % ITripMax is given in the Step Sequencing table.
Control Logic Communication is implemented via the industry standard I1, I0, and PHASE interface. This communication logic allows for full, half, and quarter step modes. Each bridge also has an independent VREF input so higher resolution step modes can be programmed by dynamically changing the voltage on the VREFx pins.
Charge Pump (CP1 and CP2) The charge pump is used to
generate a gate supply greater than the VBB in order to drive the source-side DMOS gates. A 0.1 F ceramic capacitor should be connected between CP1 and CP2 for pumping purposes. A 0.1 F ceramic capacitor is required between VCP and VBBx to act as a reservoir to operate the high-side DMOS devices.
Shutdown In the event of a fault (excessive junction temperature, or low voltage on VCP), the outputs of the device are disabled until the fault condition is removed. At power-up, the undervoltage lockout (UVLO) circuit disables the drivers.
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A3988
Quad DMOS Full Bridge PWM Motor Driver
Mixed Decay Operation The bridges operate in mixed
decay mode. Referring to figure 2, as the trip point is reached, the device goes into fast decay mode for 30.1% of the fixed off-time period. After this fast decay portion, tFD , the device switches to slow decay mode for the remainder of the off-time. During transitions from fast decay to slow decay, the drivers are forced off for approximately 600 ns. This feature is added to prevent shoot-through in the bridge. As shown in figure 2, during this "dead time" portion, synchronous rectification is not active, and the device operates in fast decay and slow decay only.
Synchronous Rectification When a PWM-off cycle is
triggered by an internal fixed off-time cycle, load current will recirculate. The A3988 synchronous rectification feature will turn on the appropriate MOSFETs during the current decay, and effectively short out the body diodes with the low RDS(on) driver. This significantly lowers power dissipation. When a zero current level is detected, synchronous rectification is turned off to prevent reversal of the load current.
VPHASE
+ IOUT See Enlargement A 0
-
Enlargement A
Fixed Off-Time 30 s 9 s 21 s
ITrip
IOUT
FDSR FDDT SDDT
SDSR SDDT
Figure 2. Mixed Decay Mode Operation
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A3988
Quad DMOS Full Bridge PWM Motor Driver
Step Sequencing Diagrams
100.0 66.7 100.0
66.7
Phase 1 (%)
0
Phase 1 (%)
0
-66.7 -66.7 -100.0 -100.0
100.0 66.7
100.0
66.7
Phase 2 (%)
0
Phase 2 (%)
0
-66.7 -66.7 -100.0 -100.0
Full step 2 phase Modified full step 2 phase
Half step 2 phase Modified half step 2 phase
Figure 3. Step Sequencing for Full-Step Increments.
Figure 4. Step Sequencing for Half-Step Increments.
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A3988
100.0
Quad DMOS Full Bridge PWM Motor Driver
66.7
33.3
Phase 1 (%)
0
-33.3
-66.7
-100.0
100.0
66.7
33.3
Phase 2 (%)
0
-33.3
-66.7
-100.0
Figure 5. Step Sequence for Quarter-Step Increments
Step Sequencing Settings
Full 1/2 1 1/4 Phase 1 (%ITripMax) 0 33 66*/100 100 100 100 66*/100 33 0 33 66*/100 100 100 100 66*/100 33 I0x H L H L L L H L H L H L L L H L I1x H H L*/H L L L L*/H H H H L*/H L L L L*/H H PHASE x 1 1 1 1 1 1 1 x 0 0 0 0 0 0 0 Phase 2 (%ITripMax) 100 100 66*/100 33 0 33 66*/100 100 100 100 66*/100 33 0 33 66*/100 100 I0x L L H L H L H L L L H L H L H L I1x L L L*/H H H H L*/H L L L L*/H H H H L*/H L PHASE 1 1 1 1 X 0 0 0 0 0 0 0 X 1 1 1 1 2 1 2 3 4 3 5 6 2 4 7 8 5 9 10 3 6 11 12 7 13 14 4 8 15 16 * Denotes modified step mode
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A3988
Quad DMOS Full Bridge PWM Motor Driver
Applications Information
Motor Configurations For applications that require either a stepper/dc motor driver or dual dc motor driver, Allegro offers the A3989 and A3995. These devices are offered in the same 36 pin QFN package as the A3988. The dc motor drivers are capable of supplying 2.4 A at 36 V. Commutation is done with a standard phase/enable logic interface. Please refer to the Allegro website for further information and datasheets about those devices. DC Motor Control Each of the 4 full bridges has independent PWM current control circuitry that makes the A3988 capable of driving up to four dc motors at currents up to 1.2 A. Control of the dc motors is accomplished by tying the I0, I1 pins together creating an equivalent ENABLE function with maximum current defined by the voltage on the corresponding VREF pin. The dc motors can be driven via a PWM signal on this enable signal, or on the corresponding PHASE pin. Motor control includes forward, reverse, and coast. Layout The printed circuit board should use a heavy groundplane. For optimum electrical and thermal performance, the A3988 must be soldered directly onto the board. On the underside of the A3988 package is an exposed pad, which provides a path for enhanced thermal dissipation. The thermal pad should be soldered directly to an exposed surface on the PCB. Thermal vias
VBB CVCP GND GND CCP CIN3
are used to transfer heat to other layers of the PCB. Grounding In order to minimize the effects of ground bounce and offset issues, it is important to have a low impedance singlepoint ground, known as a star ground, located very close to the device. By making the connection between the exposed thermal pad and the groundplane directly under the A3988, that area becomes an ideal location for a star ground point. A low impedance ground will prevent ground bounce during high current operation and ensure that the supply voltage remains stable at the input terminal. The recommended PCB layout shown in the diagram below, illustrates how to create a star ground under the device, to serve both as low impedance ground point and thermal path.
DFN Device
Solder Trace (2 oz.) Signal (1 oz.) Ground (1 oz.) Thermal (2 oz.)
PCB Thermal Vias
VBB CVCP CCP CIN3
VCP
CP2
CP1
GND
I03
I02
I01
I11
RS1 OUT1A OUT1B U1
RS3 OUT3A OUT3B
1
I04 OUT1A SENSE1
I12 I13 OUT3A
A3988
PAD
SENSE3 OUT3B VBB2 OUT4B SENSE4 OUT4A I14 PHASE2 PHASE1
RS1 CIN1
CIN1 OUT2B OUT2A RS2 CVDD1 GND VDD CVDD2 RS4 CIN2 OUT4B OUT4A
OUT1B VBB1 OUT2B SENSE2 OUT2A PHASE4 PHASE3 VREF1 VREF2
RS3 CIN2 RS4
RS2
VREF3
VREF4
CVDD1
EV package layout shown
CVDD2
Figure 6. Printed circuit board layout with typical application circuit, shown at right. The copper area directly under the A3988 (U1) is soldered to the exposed thermal pad on the underside of the device. The thermal vias serve also as electrical vias, connecting it to the ground plane on the other side of the PCB , so the two copper areas together form the star ground.
GND
VDD
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A3988
Quad DMOS Full Bridge PWM Motor Driver
additional voltage drops, adversely affecting the ability of the comparators to accurately measure the current in the windings. As shown in the layout below, the SENSEx pins have very short traces to the RSx resistors and very thick, low impedance traces directly to the star ground underneath the device. If possible, there should be no other components on the sense circuits. Note: When selecting a value for the sense resistors, be sure not to exceed the maximum voltage on the SENSEx pins of 500 mV.
The two input capacitors should be placed in parallel, and as close to the device supply pins as possible. The ceramic capacitor should be closer to the pins than the bulk capacitor. This is necessary because the ceramic capacitor will be responsible for delivering the high frequency current components. Sense Pins The sense resistors, RSx, should have a very low impedance path to ground, because they must carry a large current while supporting very accurate voltage measurements by the current sense comparators. Long ground traces will cause
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A3988
Quad DMOS Full Bridge PWM Motor Driver
Pin-out Diagrams
33 SENSE3 28 SENSE4 34 OUT3A 32 OUT3B 29 OUT4B 27 OUT4A 31 VBB2 36 NC 35 NC 30 NC 26 NC
Package EV
25 SENSE3 21 SENSE4 26 OUT3A 24 OUT3B 22 OUT4B 20 OUT4A 23 VBB2 27 I13 19 I14
Package JP
I13 37 I12 38
18 17 16 PAD 15 14 13 12 11 10 1 2 3 4 5 6 7 8 9 PHASE1 PHASE2 GND VREF4 VREF3 VREF2 VREF1 VDD PHASE3
25 NC
24 23 22 21 20 PAD 19 18 17 16 15 14 13
I14 NC PHASE1 PHASE2 GND VREF4 VREF3 VREF2 VREF1 VDD PHASE3 PHASE4
I12 28 I11 29 GND 30 VCP 31 CP1 32 CP2 33 I01 34 I02 35 I03 36
I11 39 GND 40 NC 41
Packages are not to scale
VCP 42 CP1 43 CP2 44 I01 45 I02 46 I03 47 I04 48
OUT1A
OUT1B
SENSE1
OUT2B
SENSE2
OUT2A
VBB1
I04
PHASE4
OUT2A 10
OUT1A
OUT1B
VBB1
SENSE1
OUT2B
Terminal List Table
EV 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 1 - - Number JP 3 4 5 6 8 9 10 13 14 15 16 17 18 19 20 2 22 24 27 28 29 31 32 33 34 37 38 39 40 42 43 44 45 46 47 48 1, 2, 7, 11, 12, 23, 25, 26, 30, 35, 36, 41 - Pin Name OUT1A SENSE1 OUT1B VBB1 OUT2B SENSE2 OUT2A PHASE4 PHASE3 VDD VREF1 VREF2 VREF3 VREF4 GND PHASE2 PHASE1 I14 OUT4A SENSE4 OUT4B VBB2 OUT3B SENSE3 OUT3A I13 I12 I11 GND VCP CP1 CP2 I01 I02 I03 I04 NC PAD Pin Description
DMOS Full-Bridge 1 Output A Sense Resistor Terminal for Bridge 1 DMOS Full-Bridge 1 Output B Load Supply Voltage DMOS Full-Bridge 2 Output B Sense Resistor Terminal for Bridge 2 DMOS Full-Bridge 2 Output A Control Input Control Input Logic Supply Voltage Analog Input Analog Input Analog Input Analog Input Ground Control Input Control Input Control Input DMOS Full-Bridge 4 Output A Sense Resistor Terminal for Bridge 4 DMOS Full-Bridge 4 Output B Load Supply Voltage DMOS Full-Bridge 3 Output B Sense Resistor Terminal for Bridge 3 DMOS Full-Bridge 3 Output A Control Input Control Input Control Input Ground Reservoir Capacitor Terminal Charge Pump Capacitor Terminal Charge Pump Capacitor Terminal Control Input Control Input Control Input Control Input No Connect Exposed pad for enhanced thermal performance. Should be soldered to the PCB.
SENSE2
NC 12
NC 11
1
2
3
4
5
6
7
8
NC
NC
NC
9
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A3988
Quad DMOS Full Bridge PWM Motor Driver
EV Package, 36 Pin QFN with Exposed Thermal Pad
Preliminary dimensions, for reference only (reference JEDEC MO-220VJJD-1, except exposed thermal pad) Dimensions in millimeters U.S. Customary dimensions (in.) in brackets, for reference only Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area B Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) C Reference land pattern layout (reference IPC7351 QFN50P600X600X100-37V1M); adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
6.15 .242 5.85 .230 36 1 2 A
A B
6.15 .242 5.85 .230
36X 0.08 [.003] C 36X 0.30 .012 0.18 .007 0.10 [.004] M C A B 0.05 [.002] M C
SEATING PLANE 1.00 .039 0.80 .031 0.50 .020 0.20 .008 REF 0.05 .002 0.00 .000
C
0.25 .010 NOM 1.15 .045 NOM 1 2 4X0.20 .008 MIN 36
32X0.20 .008 MIN 0.50 .020 NOM
0.75 .030 0.35 .014
C 4.15 .163 NOM
5.8 .228 NOM R0.30 .012 REF
4.15 .163 NOM 2 1 36
4X0.20 .008 MIN
4.15 .163 NOM 5.8 .228 NOM
4.15 .163 NOM
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A3988
Quad DMOS Full Bridge PWM Motor Driver
JP Package, 48 Pin LQFP with Exposed Thermal Pad
0.30 .012 NOM 1.85 .073 NOM
44X0.20 .008 MIN 0.50 .020 NOM B A 9.20 .362 8.80 .346 7.20 .283 6.80 .268 7 0 0.20 .008 0.09 .004
C 5.10 .201 NOM 8.5 .335 NOM
9.20 .362 8.80 .346 7.20 .283 6.80 .268
B
5.10 .201 NOM 0.75 .030 0.45 .018
48 48
A
1 .039 REF
1 12 5.10 .201 NOM .008 8.5 .335 NOM
2 5.10 .201 NOM 0.25 .010 SEATING PLANE GAGE PLANE
4X0.20 MIN
4X0.20 MIN
.008
48X 0.08 [.003] C 48X 0.27 .011 0.17 .007 0.08 [.003] M C B A Dimensions reference only, not for tooling use (reference JEDEC MS-026 BBCHD) Dimensions in millimeters U.S. Customary dimensions (in.) in brackets, for reference only Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown 0.50 .020
SEATING PLANE
C
A Terminal #1 mark area B Exposed thermal pad (bottom surface)
1.60 .063 MAX 1.45 .057 1.35 .053 0.15 .006 0.05 .002
C Reference land pattern layout (reference IPC7351 TSQFP50P900X900X160-48M); adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Use of any Allegro product in any Aerospace or Aviation application is strictly prohibited. Allegro's products may only be used in life support devices or systems with the express written approval of an Allegro Vice President, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. Copyright (c)2006, 2007, Allegro MicroSystems, Inc. For the latest version of this document, visit our website: www.allegromicro.com
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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